Regular Sessions
Session 1: Design Techniques for Industrial Applications
Session Chair: Jinwook Oh, RebellionSession Co-chair: Po-Hung Lin, National Yang Ming Chiao Tung University
Date: Nov. 07, 2022 (Monday)
Time: 10:50 – 12:30 (UTC+8)
Room: Auditorium 國際會議廳, 10F
| ID | Time | Title / Authors / Affiliation |
| 1.1 (7033) (Highlight) |
10:50 | 11:15 |
Energy Efficient BNN Accelerator using CiM and a TimeInterleaved Hadamard Digital GRNG in 22nm CMOS Richard Dorrance, Deepak Dasalukunte, Hechen Wang, Renzhi Liu, Brent Carlton Intel Corporation, USA |
| 1.2 (7176) (Highlight) |
11:15 | 11:40 |
Sub-GHz RF Energy Harvester including a Small Loop
Antenna Darshan Shetty1, Christoph Steffan1, Wolfgang Bösch2, Jasmin Grosinger2 1Infineon Technologies AG, Austria 2Graz University of Technology, Austria |
| 1.3 (7022) (Highlight) |
11:40 | 12:05 |
An Attachable Fractional Divider Transforming an
Integer-N PLL Into a Fractional-N PLL with SSC Capability Atsushi Motozawa, Yasuyuki Hiraku, Yoshitaka Hirai, Naoaki Hiyama, Yusuke Imanaka, Fukashi Morishita Renesas Electronics Corporation, Japan |
| 1.4 (7024) (Highlight) |
12:05 | 12:30 |
A Learning-Based Algorithm for Early Floorplan With
Flexible Blocks 1JEN-WEI LEE, 1YI-YING LIAO, 1TE-WEI CHEN, 1YU-HSIU LIN, 1CHIA-WEI CHEN, 1CHUN-KU TING, 1SHENG-TAI TSENG, 1RONALD KUO-HUA HO, 1HSIN-CHUAN KUO, 1CHUN-CHIEH WANG, 1MING-FANG TSAI, 1CHUN-CHIH YANG, 1TAI-LAI TUNG, and 2DA-SHAN SHIU 1MediaTek, Taiwan 2MediaTek Research, Taiwan |
Session 2: Switching Mode Power Converters
Session Chair: Makoto Takamiya, University of TokyoSession Co-chair: Wanyuan Qu, Zhejiang University
Date: Nov. 07, 2022 (Monday)
Time: 14:00 – 15:40 (UTC+8)
Room: Auditorium 國際會議廳, 10F
| ID | Time | Title / Authors / Affiliation |
| 2.1 (7081) |
14:00 | 14:25 |
A Single-inductor Triple-output Buck DC-DC Converter
with Electromagnetic Gated Low Dropouts for Higher
Resistance to Electromagnetic and Power Side-Channel
Attacks with 3B Minimum Traces to Disclosure
Improvement in Internet of Things Applications Ya-Ting Hsu1, Yu-Jheng Ouyang1, Ke-Horng Chen1, Kuo-Lin Zheng2, Ying-Hsi Lin3, Shian-Ru Lin3, and Tsung-Yen Tsai3 1National Yang Ming Chiao Tung University, Taiwan 2Chip-GaN Power Semiconductor Corporation, Taiwan 3Realtek Semiconductor Corp, Taiwan |
| 2.2 (7046) |
14:25 | 14:50 |
An One-Cycle Load Transient Response and 0.81 mV/A
Load-Regulation Time-Domain Cascaded-VCOControlled Buck Converter for Powering Gaming SoC Chieh-Ju Tsai1, I-Fang Lo2, Tsung-Hsien Lin1, Ching-Jan Chen1 1National Taiwan University, Taiwan 2Richtek Technology Corporation, Taiwan |
| 2.3 (7038) |
14:50 | 15:15 |
A 90.6% Peak-Efficiency 1.5A Dual Inductor Ladder BuckConverter Achieving 0.93W/mm2 Active Peak Power Density for Li-ion Battery Operated PMICs Arindam Mishra, Wei Zhu, and Valentijn De Smedt ESAT, ADVISE, KU Leuven, Belgium |
| 2.4 (7108) |
15:15 | 15:40 |
A 96.62%-Peak-Efficiency and Seamless-Mode-Transition
Buck-Boost DC-DC Converter with Auto-Shift-Ramp Chi-Wei Chen, Bao-Xian Peng, and Hsin-Shu Chen National Taiwan University, Taiwan |
Session 3: Novel Neural Network and Crypto Processors
Session Chair: Kun-Chih Chen, National Sun Yat-Sen UniversitySession Co-chair: Leibo Liu, Tsinghua University
Date: Nov. 07, 2022 (Monday)
Time: 14:00 – 15:40 (UTC+8)
Room: Song Bo 松柏廳, 10F
| ID | Time | Title / Authors / Affiliation |
| 3.1 (7065) (Highlight) |
14:00 | 14:25 |
SNPU: Always-on 63.2µW Face Recognition Spike Domain
Convolutional Neural Network Processor with Spike Train
Decomposition and Shift-and-Accumulation Unit Sangyeob Kim, Sangjin Kim, Soyeon Um, Soyeon Kim, Juhyoung Lee and Hoi-Jun Yoo Korea Advanced Institute of Science and Technology, Korea |
| 3.2 (7042) (Highlight) |
14:25 | 14:50 |
A 28nm 57.6TOPS/W Attention-based NN Processor with
Correlative Computing-in-Memory Ring and Dataflowreshaped Digital-assisted Computing-in-Memory Array Ruiqi Guo1, Zhiheng Yue1, Hao Li1, Te Hu1, Yabing Wang1, Hao Sun1, Jeng-Long Hsu2, Yaojun Zhang3, Bonan Yan4, Leibo Liu1, Ru Huang4, Shaojun Wei1, Shouyi Yin1 1Tsinghua University, China 2NeoNexus Pte. Ltd., Singapore 3Pimchip Technology Co., Ltd., China 4Peking University, China |
| 3.3 (7170) |
14:50 | 15:15 |
A 65nm 8-bit All-Digital Stochastic-Compute-In-Memory
Deep Learning Processor Jiyue Yang, Tianmu Li, Wojciech Romaszkan, Puneet Gupta, and Sudhakar Pamarti University of California, Los Angeles, USA |
| 3.4 (7188) |
15:15 | 15:40 |
High-speed and energy-efficient crypto-processor for
post-quantum cryptography CRYSTALS-Kyber Taishin Shimada, Makoto Ikeda The University of Tokyo, Japan |
Session 4: RF Transceiver Techniques
Session Chair: Chien-Nan Kuo, National Yang Ming Chiao Tung UniversitySession Co-chair: Baoyong Chi, Tsinghua University
Date: Nov. 07, 2022 (Monday)
Time: 14:00 – 15:40 (UTC+8)
Room: Chang Chin 長青廳, 10F
| ID | Time | Title / Authors / Affiliation |
| 4.1 (7023) (Highlight) |
14:00 | 14:25 |
A 110-120-GHz, 12.2% Efficiency, 16.2-dBm Output Power
Multiplying Outphasing Transmitter in 22-nm FDSOI Jeff Shih-Chieh Chien, James F. Buckwalter University of California, Santa Barbara, USA |
| 4.2 (7027) |
14:25 | 14:50 |
A D-Band Packaged CMOS Integrated Transmitter for MUMIMO Applications Meng Wei1, Nima Baniasadi1, Ethan Chou1, Hesham Beshary1, Sashank Krishnamurthy2, Elad Alon1, Ali Niknejad1 1University of California, Berkeley, USA 2Intel, USA |
| 4.3 (7050) (Highlight) |
14:50 | 15:15 |
A Dual-Band 2×2 802.11ax Transceiver Supporting
160MHz CBW and 1024-QAM Chao Lu1, Shr-Lung (Calvin) Chen2, Jun Liu3, Jian Bao3, Yi Zhao3, Chin-Ming Chien2, Yufei Wang1, Jianqiu Chen3, Zexin Liao3, BingDing3, Bihui Zhu3, Jinhua Chen3, Pengfei Yue3, Ran Wang3, and Chun Wang3 1ASR Microelectronics Inc., USA 2ASR Microelectronics Inc., USA 3ASR Microelectronics Ltd., China |
| 4.4 (7141) |
15:15 | 15:40 |
A 32.2-38.2 GHz Broadband 4-Channel TRx Beamformer
with Embedded 3-Winding Transformer Based PA/LNA
FE and High Resolution Phase/Amplitude Control Yongjie Li1, Zongming Duan1, Xiao Li1, Chuanming Zhu1, Na Ding1, Yuefei Dai1, Liguo Sun2, Hao Gao3 1East China Research Institute of Electronic Engineering, China 2University of Science and Technology of China, China 3Eindhoven University of Technology, the Netherlands |
Session 5: Biomedical Sensing Chips and Systems
Session Chair: Philex Ming-Yan Fan, National Cheng Kung UniversitySession Co-chair: Bo Zhao, Zhejiang University
Date: Nov. 07, 2022 (Monday)
Time: 14:00 – 15:40 (UTC+8)
Room: V110 十全軒, VF
| ID | Time | Title / Authors / Affiliation |
| 5.1 (7198) (Highlight) |
14:00 | 14:25 |
A Synchronous-Sampling Impedance-Readout IC with
Baseline-Cancellation-Based Two-Step Conversion for
Fast Neural Electrical Impedance Tomography Ji-Hoon Suh1, Haidam Choi1, Yoontae Jung1, Sein Oh1, Hyungjoo Cho1, Nahmil Koo2, Seong Joong Kim2, Chisung Bae2, Sohmyung Ha3, and Minkyu Je1 1KAIST, Korea 2Samsung Advanced Institute of Technology, Korea 3New York University Abu Dhabi, United Arab Emirates |
| 5.2 (7120) |
14:25 | 14:50 |
A 1984-Pixels, 1.26nW/Pixel Retinal Prosthesis Chip with
Time-Domain In-Pixel Image Processing Dong-Hwi Choi and Dong-Woo Jee Ajou University, Korea |
| 5.3 (7074) |
14:50 | 15:15 |
A 64-channel back-gate adapted ultra-low-voltage spikeaware neural recording front-end with on-chip
lossless/near-lossless compression engine and 3.3V
stimulator in 22nm FDSOI Franz Marcus Schüffny, Seyed Mohammad Ali Zeinolabedin, Richard George, Liyuan Guo, Annika Weiße, Johannes Uhlig, Julian Meyer, Andreas Dixius, Stefan Hänzsche, Marc Berthel, Stefan Scholze, Sebastian Höppner, Christian Mayr TU Dresden, Germany |
| 5.4 (7123) |
15:15 | 15:40 |
A Heart-related Physiological Signal Monitoring SoC for
Wearable ECG Analysis Systems Peng-Wei Huang 1, Shuenn-Yuh Lee1, Chieh Tsou1, Yi-Wen Hung1, Po-Han Su1, Ju-Yi Chen2 1National Cheng Kung University, Taiwan 2National Cheng Kung University Hospital, Taiwan |
Session 6: High-Speed and Time-Interleaved ADCs
Session Chair: Hsin-Shu Chen, National Taiwan UniversitySession Co-chair: Yong Lim, Samsung Electrnics
Date: Nov. 08, 2022 (Tuesday)
Time: 10:50 – 12:30 (UTC+8)
Room: Auditorium 國際會議廳, 10F
| ID | Time | Title / Authors / Affiliation |
| 6.1 (7053) (Highlight) |
10:50 | 11:15 |
A Single-Channel 14b 500 MS/s Pipelined-SAR ADC with
Reference Ripple Mitigation Techniques and AdaptiveBiased Floating Inverter Amplifier 1,2Wenning Jiang, 1Yan Zhu, 1Chi-hang Chan, and 1,3Rui Martins 1University of Macau, China 2Fudan University, Shanghai, China 3Universidade de Lisboa, Portugal |
| 6.2 (7190) |
11:15 | 11:40 |
A 3.07mW 30MHz-BW 73.5dB-SNDR Time-Interleaved
Noise-Shaping SAR ADC with 2nd
-order ErrorFeedforward and Redundancy-Bit Reduction Shulin Zhao1, Mingqiang Guo1, Sai-Weng Sin1,2, Liang Qi3, Dengke Xu4, Guoxing Wang3, Rui P. Martins1,5 1University of Macau, China 2Zhuhai UM Science & Technology Research Institute, China 3Shanghai Jiao Tong University, China 4Amicro Semiconductor Co., Ltd, China 5University of Lisboa, Portugal |
| 6.3 (7095) |
11:40 | 12:05 |
A 12b 8GS/s Time-Interleaved 2b/cycle Pipelined-SAR
ADC with Layout-Customized Bootstrap and SuperSource-Follower Based Open-Loop Residue Amplifier Qiang Yu1,2, Jie Pu1, Jian Luo1, Zhengbo Huang1, Junhong Wu1, Xing Zhu1, Feixiang Xiang1, Lei Chen1, Jianwen Li1, Qiang Li2, Jinda Yang1, and Yuanjun Cen1 1Chengdu Sino Microelectronics Technology, China 2University of Electronic Science and Technology of China, China |
| 6.4 (7225) |
12:05 | 12:17 |
A 6-bit 5.12-GS/s Flash ADC with Track-and-Hold Embedded
Dynamic Preamplifier in 28nm CMOS Daesik Moon1,2, Sangwoo Lee3, Taewoong Kim1, Woo-Young Choi1, and Youngcheol Chae1 1Yonsei University, Korea 2Samsung Electronics, Korea 3Robert Bosch LLC., USA |
| 6.5 (7213) |
12:17 | 12:30 |
A 7-Bit 4-GS/s Quad-Channel Time-Interleaved SAR ADC
With 2-Then-1-Bit/Cycle Conversion Jihyun Baek, Jonghyun Kim, Gyuchan Cho, Jintae Kim, and Hyungil Chae Konkuk University, Korea |
Session 7: Emerging Computing Applications on FPGA
Session Chair: Chuen-Yau Chen, National University of KaohsiungSession Co-chair: Youngjoo Lee, POSTECH
Date: Nov. 08, 2022 (Tuesday)
Time: 10:50 – 12:30 (UTC+8)
Room: Song Bo 松柏廳, 10F
| ID | Time | Title / Authors / Affiliation |
| 7.1 (7254) (Highlight) |
10:50 | 11:15 |
A 75.6M Base-pairs/s FPGA Accelerator for FM-index
Based Paired-end Short-Read Mapping Chung-Hsuan Yang1, Yi-Chung Wu1, Yen-Lung Chen1, Chao-Hsi Lee2, Jui-Hung Hung2,3, Chia-Hsiang Yang1,2 1National Taiwan University, Taiwan 2GeneASIC Technologies Corp., Taiwan 3National Yang Ming Chiao Tung University, Taiwan |
| 7.2 (7152) |
11:15 | 11:40 |
A 217.8 MSOPs/W FPGA-based Online Learning SNN
Processor Using Unified Event-Driven Structure and
Topology Aware Data Reuse Strategies Chaoming Fang1,2, Fengshi Tian2, Chuanqing Wang2, Jie Yang2, Mohamad Sawan2 1Zhejiang University, China 2CenBRAIN Neurotech, Westlake University, China |
| 7.3 (7187) |
11:40 | 12:05 |
A Flexible Instruction-based Post-quantum Cryptographic Processor with Modulus Reconfigurable
Arithmetic Unit for Module LWR&E Aobo Li, Dongsheng Liu, Xiang Li, Tianze Huang, Shuo Yang, Jiahao Lu, Ang Hu Huazhong University of Science and Technology, China |
| 7.4 (7100) |
12:05 | 12:30 |
Method of Halved Interaction Elements with Regularity
Arrangement that achieves Independent Double Systems
for Scalable Fully Coupled Annealing Processing Shinjiro Kitahara, Akari Endo, Taichi Megumi, and Takayuki Kawahara Tokyo University of Science, Katsushika, Japan |
Session 8: High Performance Receiver and Detection Techniques
Session Chair: Kuang-Wei Cheng, National Cheng Kung UniversitySession Co-chair: Dixian Zhao, Southeast University
Date: Nov. 08, 2022 (Tuesday)
Time: 10:50 – 12:30 (UTC+8)
Room: Chang Chin 長青廳, 10F
| ID | Time | Title / Authors / Affiliation |
| 8.1 (7214) (Highlight) |
10:50 | 11:15 |
A 37-39GHz Phase and Amplitude Detection Circuit with
0.060 degree and 0.043dB RMS Errors for the Calibration
of 5GNR Phased-Array Beamforming Yudai Yamazaki, Jun Sakamaki, Jian Pang, Joshua Alvin, Zheng Li, Atsushi Shirane, Kenichi Okada Tokyo Institute of Technology, Japan |
| 8.2 (7074) |
11:15 | 11:40 |
A 0.55mm2
16.9mW Fully Integrated 0-to-200MHz System
BW Wireless Direct Sampling Receiver in 14nm FinFET Ilhoon Jang, Barosaim Sung, Jaehoon Lee, Soonwoo Choi, Byoungjoong Kang, Suseob Ahn, Kyungmin Lee, Taejin Jang, Kwangmin Lim, Anna Yu, Yong Lim, Seunghyun Oh, and Jongwoo Lee Samsung Electronics, Korea |
| 8.3 (7124) |
11:40 | 12:05 |
An n79 Sub-1-dB Noise Figure Highly Linear VariableGain LNA Employing Adaptive Imbalanced Bleeding for
5G NR Jinglong Xu1, Keun-Mok Kim1, Hafiz Usman Mahmood1, Jusung Kim2, Sang-Gug Lee1 1KAIST, Korea 2Hanbat National University, Korea |
| 8.4 (7232) |
12:05 | 12:30 |
A 24GHz CMOS UWB Radar IC with IQ Correlation
Receiver for Short Range Human Detection Dongwuk Park1,2, Byeongjae Seo1, Kiryun Byeon1, Gu Jung2, andYunseong Eo1,2 1Kwangwoon University, Korea 2Silicon R&D, Corp., Korea |
Session 9: Energy-Efficient Digital Circuit Techniques
Session Chair: Amit Agarwal, IntelSession Co-chair: Chia-Hsiang Yang, National Taiwan University
Date: Nov. 08, 2022 (Tuesday)
Time: 10:50 – 12:30 (UTC+8)
Room: V110 十全軒, VF
| ID | Time | Title / Authors / Affiliation |
| 9.1 (7154) (Highlight) |
10:50 | 11:15 |
DSC-TRCP: Dynamically Self-calibrating Tunable Replica
Critical Paths Timing Monitoring for Variation Resilient
Circuits with Low Cost & Large Power/Frequency Gain Zhengguo Shen, Weiwei Shan*, Yuxuan Du, Ziyu Li, Chengjun Wu, Jun Yang Southeast University, China |
| 9.2 (7208) |
11:15 | 11:40 |
C3MLS: A 0.12-nW Leakage and 18.11-fJ/Transition Level
Shifter With Cross-Coupled and Current Mirror Hybrid
Structure for Ultra-Wide Range Level Conversions Cong Huang and Hailong Jiao* Peking University, China |
| 9.3 (7117) |
11:40 | 12:05 |
A 0.0043-mm2 Capacitorless External-Clock-Free FullySynthesizable Digital LDO Using Load-Direct Droop
Detector and Time-Based Load-State Decision Jonghyun Oh1, Yoonho Song2, Young-Ha Hwang3, Jun-Eun Park4, Mingoo Seok1, and Deog-Kyoon Jeong2 1Columbia University, USA 2Seoul National University, Korea 3Soongsil University, Korea 4Chungnam National University, Korea |
| 9.4 (7168) |
12:05 | 12:17 |
A 10-Gbps, 0.121-pJ/bit, All-Digital True Random-Number
Generator using Middle Square Method Jonghyun Kim and Hyungil Chae Konkuk University, Korea |
| 9.5 (7157) |
12:17 | 12:30 |
A Variation-Tolerant Differential Contention-Free Pulsed
Latch with Wide Voltage Scalability Gicheol Shin, Minhyeok Jeong, Donguk Seo, Shin Han, Yoonmyung Lee Sungkyunkwan University, Korea |
Session 10: Analog Techniques
Session Chair: Tetsuya Hirose, Osaka UniversitySession Co-chair: Mustafijur Rahman, Indian Institute of Technology Delhi
Date: Nov. 08, 2022 (Tuesday)
Time: 14:00 – 15:40 (UTC+8)
Room: Auditorium 國際會議廳, 10F
| ID | Time | Title / Authors / Affiliation |
| 10.1 (7132) (Highlight) |
14:00 | 14:25 |
A Process-Scalable Ultra-Low-Voltage 180kHz Sleep
Timer with a Time-Domain Amplifier and a Switch-less
Resistance Multiplier Chongsoo Jung1, Hoyong Seong1, Injun Choi1, Sohmyung Ha2, and Minkyu Je1 1KAIST, Korea 2New York University Abu Dhabi, United Arab Emirates |
| 10.2 (7068) |
14:25 | 14:50 |
A sub-0.5V Crystal Oscillator-Timer (XO-Timer) Combining
16MHz Reference and 32kHz Sleep Timer with a Single
Crystal for Energy-Harvesting Radios in 28nm CMOS Liwen Lin1, Ka-Meng Lei1, Pui-In Mak1, Rui P.Martins1,2 1University of Macau, China 2Universidade de Lisboa, Portugal |
| 10.3 (7077) |
14:50 | 15:15 |
A 0.63-mm2/Ch 1.3-mΩ/√Hz-Sensitivity 1-MHz
Bandwidth Active Electrode Electrical
Impedance Tomography System Ting Zhou, Hui Li, Jiajie Huang, Chao Wang, Qianyu Guo, Junyan Liu, Zhiwen Gu, Yang Zhao, Jian Zhao, Mingyi Chen, Yan Liu, Guoxing Wang, Yong Lian, Yongfu Li* Shanghai Jiao Tong University, China |
| 10.4 (7189) |
15:15 | 15:40 |
A 1.7-6.4 GHz fourth-order RF filter with 1-40% fractional
bandwidth in 22-nm FDSOI Iman Ghotbi, Baktash Behmanesh, and Markus Törmänen Lund University, Sweden |
Session 11: Computing & Processing in Memory
Session Chair: Shyh-Shyuan Sheu, Industrial Technology Research InstituteSession Co-chair: Juang-Ying Chueh, Etron Technology Inc
Date: Nov. 08, 2022 (Tuesday)
Time: 14:00 – 15:40 (UTC+8)
Room: Song Bo 松柏廳, 10F
| ID | Time | Title / Authors / Affiliation |
| 11.1 (7061) (Highlight) |
14:00 | 14:25 |
A 28nm Hybrid 2T1R RRAM Computing-in-Memory Macro
for Energy-efficient AI Edge Inference Wang Ye1,3, Chunmeng Dou1,3, Linfang Wang1,3, Zhidao Zhou1,3, Junjie An1, Weizeng Li1,3, Hanghang Gao1,3, Xiaoxin Xu1,3, Jinshan Yue1, Jianguo Yang1,3, Jing Liu1,3, Dashan Shang1,3, Jinghui Tian2, Qi Liu1,2, Ming Liu1,2 1Institute of Microelectronics of the Chinese Academy of Sciences, China 2Fudan University, China 3University of Chinese Academy of Sciences, China |
| 11.2 (7167) (Highlight) |
14:25 | 14:50 |
A Local Transpose 9T SRAM Compute-In-Memory Macro
with Programmable Single-Slope SAR ADC Xin Zhang*1, Yongjun Jo*1, Jiahao Liu2, Jun Zhou2, Yuanjin Zheng1, and Tony Tae-Hyoung Kim1 (*Equally contributed authors) 1Nanyang Technological University, Singapore 2University of Electronic Science and Technology of China, China |
| 11.3 (7203) |
14:50 | 15:15 |
Spike-CIM: A 290TOPS/W Spike-Encoding SparsityAdaptive Computing-in-Memory Macro with Differential
Charge-Domain Integrate-and-Fire Jiahao Song1, Xiyuan Tang1, Haoyang Luo1, Kuan Xu2, Yuan Wang1, Zhigang Ji2, Runsheng Wang1, and Ru Huang1 1Peking University, China 2Shanghai Jiao Tong University, China |
| 11.4 (7245) |
15:15 | 15:27 |
A Hybrid Temperature Compensation method combined with
Digital and Analog Temperature Compensation Techniques for
3D-NAND Flash Memories Dojeon Lee, Junhong Park, Philkyu Kang, Sungmin Jo, Seheon Baek, Chi-Weon Yoon, Dongku Kang Samsung Electronics, Korea |
| 11.5 (7160) |
15:27 | 15:40 |
A Variation-Tolerant Processing-In-Memory Architecture
Using Discharging Current Calibration Daiki Kitagata, Shinji Tanaka, Naoya Fujita and Naoaki Irie Renesas Electronics Corporation, Japan |
Session 12: Advanced Wireline Transceiver Techniques
Session Chair: Wei-Zen Chen, National Yang Ming Chiao Tung UniversitySession Co-chair: Jung-Hoon Chun, Sungkyungkwan University
Date: Nov. 08, 2022 (Tuesday)
Time: 14:00 – 15:40 (UTC+8)
Room: Chang Chin 長青廳, 10F
| ID | Time | Title / Authors / Affiliation |
| 12.1 (7051) (Highlight) |
14:00 | 14:25 |
A 103 fJ/b/dB, 10-26 Gbps Receiver with a Dual Feedback
Nested Loop CDR for Wide Bandwidth Jitter Tolerance
Enhancement Yao-Chia Liu1, Wei-Zen Chen1, Yuan-Sheng Lee2, Yu-Hsiang Chen2, Shawn Min2, Ying-Hsi Lin2 1National Yang Ming Chiao Tung University, Taiwan 2Realtek Semiconductor Corp., Taiwan |
| 12.2 (7026) (Highlight) |
14:25 | 14:50 |
A 42Gb/s PAM-8 Transmitter with Feed-Forward
Tomlinson-Harashima Precoding in 28nm CMOS Byungjun Kang, Woosong Jung, Hyojun Kim, Sanghee Lee, and Deog-Kyoon Jeong Seoul National University, Korea |
| 12.3 (7228) |
14:50 | 15:15 |
A 11.4-Gbps/lane MIPI 32-bit C-PHY and D-PHY combo
transmitter with 3-tap FFE Junhan Bae1, Myeongkyu Song1, Bongkyu Kim1, Junkyu Lee1, Woosung Park1,2, and Jung-Hoon Chun1,3 1Sungkyunkwan University, Korea 2Samsung Electronics, Korea 3SolidVue, Korea |
| 12.4 (7226) |
15:15 | 15:40 |
A 5.0-to-12.5-Gb/s, 1.7-pJ/b, 0.66-µs Lock-time Referenceless Sub-sampling CDR with Beat Detection FLL in 28nm CMOS Woosung Park1, 2, Jahoon Jin2, Minsu Park1, Sangdon Jung1, 2, and Jung-Hoon Chun1, 3 1Sungkyunkwan University, South Korea 2Samsung Electronics, South Korea 3SolidVue, South Korea |
Session 13: Communication and Powering Techniques for Biomedical Applications
Session Chair: Youngcheol Chae, Yonsei UniversitySession Co-chair: Inhee Lee, University of Pittsburgh
Date: Nov. 08, 2022 (Tuesday)
Time: 14:00 – 15:40 (UTC+8)
Room: V110 十全軒, VF
| ID | Time | Title / Authors / Affiliation |
| 13.1 (7025) (Highlight) |
14:00 | 14:25 |
A 20-MHz 2.3-mW Receiver and a 25-V Transmitter for
Ultrasound Capsule Endoscopy Kyeongwon Jeong1, Jaesuk Choi1, Gichan Yun1, Injun Choi1, Jeehoon Son2, Jae Youn Hwang2, Sohmyung Ha3, and Minkyu Je1 1KAIST, Korea 2DGIST, Korea 3New York University Abu Dhabi, United Arab Emirates |
| 13.2 (7159) |
14:25 | 14:50 |
An Intra-Body-Power-Transfer System with a PLL-based
Continuous Maximum Resonant Power Tracking Loop at
TX and 1.8V DC Output Voltage at RX Hyungjoo Cho1, Ji-Hoon Suh1, Gichan Yun1, Sohmyung Ha2, and Minkyu Je1 1KAIST, Korea 2New York University Abu Dhabi, United Arab Emirates |
| 13.3 (7163) |
14:50 | 15:15 |
A 2m-Range 711uW Body Channel Communication
Transceiver Featuring Dynamically-Sampling Bias-Free
Interface Front End Guanjie Gu1, Changgui Yang1, Zhuhao Li1, Xiangdong Feng1, Ziyi Chang1, Ting-Hsun Wang1, Yunshan Zhang1, Yuxuan Luo1, Hong Zhang1, Ping Wang1, Sijun Du2, Yong Chen3, and Bo Zhao1* 1Zhejiang University, China 2Delft University of Technology, Netherlands 3University of Macau, China * Corresponding Author: Bo Zhao (zhaobo@zju.edu.cn) |
| 13.4 (7169) |
15:15 | 15:40 |
A Low-power Sleep Apnea Monitoring IC with a Duty-Recovered Body Channel Communication Receiver Pangi Park, Donghyeok Cho, SeongHwan Cho KAIST, Korea |
Session 14: LDO Voltage Regulators
Session Chair: Hyun-Sik Kim, KAISTSession Co-chair: Hyungil Chae, Konkuk University
Date: Nov. 09, 2022 (Wednesday)
Time: 09:00 – 10:40 (UTC+8)
Room: Auditorium 國際會議廳, 10F
| ID | Time | Title / Authors / Affiliation |
| 14.1 (7085) |
09:00 | 09:25 |
A Digital LDO in 22nm CMOS with a 4b Self-triggered
Binary Search Windowed Flash ADC Featuring Automatic
Analog Layout Generator Framework Xiaosen Liu1,2, Soner Yaldiz2, Parijat Mukherjee2, Steven Burns2, Harish Krishnamurthy2, Krishnan Ravichandran2, Zakir Ahmed2, Nachiket Desai2, Nicolas Butzen2, James Tschanz2, Vivek De2 1Tsinghua University, School of Integrated Circuits, China 2Intel Corporation, U.S.A |
| 14.2 (7086) |
09:25 | 09:50 |
A Fast-Transient and Wide-Range Output Capacitor-Less
NMOS LDO Regulator with Adaptive-Gain Nested Miller
Compensation and Pre-Emphasis Inverse Biasing Hyunjun Park, Woojoong Jung, Minsu Kim, and Hyung-Min Lee Korea University, Korea |
| 14.3 (7144) |
09:50 | 10:15 |
A Capacitor-less Digital LDO using Ripple-FrequencyAdaptive Time-domain Digital Pre-distortion Technique Angxiao Yan1, Wei Deng1,2, Haikun Jia1, Shiwei Zhang1, Rui Wu3, Zhihua Wang1,2, and Baoyong Chi1 1singhua University, China 2Research Institute of Tsinghua University in Shenzhen, China 3National Key Lab of Microwave Imaging Technology, AIR, CAS, China |
| 14.4 (7072) |
10:15 | 10:40 |
A Self-Clocked TDC-Based Unified Clock and Voltage
Regulator with Replica Frequency-Locked Loop and
Hysteresis Switching in 65nm CMOS Xuliang Wang, Wing-Hung Ki, and Philip K. T. Mok The Hong Kong University of Science and Technology, China |
Session 15: Energy-Efficient Machine Learning Processors and High-Speed Interface
Session Chair: Yu-Guang Chen, National Central UniversitySession Co-chair: Chao Wang, Huazhong University of Science and Technology
Date: Nov. 09, 2022 (Wednesday)
Time: 09:00 – 10:40 (UTC+8)
Room: Song Bo 松柏廳, 10F
| ID | Time | Title / Authors / Affiliation |
| 15.1 (7145) (Highlight) |
09:00 | 09:25 |
A 2.47 μJ/sample QR-Decomposition-based Extreme
Learning Machine Engine Supporting Online Class
Incremental Learning for ECG-based User Identification Yi-Ta Chen, Li-Sheng Chang, Yu-Chuan Chuang, An-Yeu Wu National Taiwan University, Taiwan |
| 15.2 (7215) (Highlight) |
09:25 | 09:50 |
A 1.3mW Speech-to-Text Accelerator with Bidirectional
Light Gated Recurrent Units for Edge AI Yu-Hsuan Tsai*1, Yi-Cheng Lin*1, Wen-Ching Chen2, Liang-Yi Lin2, Nian-Shyang Chang2, Chun-Pin Lin2, Shi-Hao Chen3, Chi-Shi Chen2, and Chia-Hsiang Yang1 1National Taiwan University, Taiwan 2Taiwan Semiconductor Research Institute, Taiwan 3Digwise Technology Ltd., Taiwan *Equally-Credited Authors (ECAs) |
| 15.3 (7166) |
09:50 | 10:15 |
A 6 Gbps PAM-3 Transceiver with Time-Varying Offset
Compensation Ju Eon Kim1,2, Dong-Hyun Yoon2, Junyoung Song3, Kwang-Hyun Baek4, Jung-Hwan Choi1, and Tony Tae-Hyoung Kim2 1Samsung Electronics, Korea 2Nanyang Technological University, Singapore 3Incheon National University, Korea 4Chung-Ang University, Korea |
| 15.4 (7147) |
10:15 | 10:40 |
A 12.8-Gbps 0.5-pJ/b Encoding-less Inductive Coupling
Interface Using Clocked Hysteresis Comparator for 3Dstacked SRAM in 7-nm FinFET Kota Shiba1, Mitsuji Okada2, Atsutake Kosuge2, Mototsugu Hamada2, and Tadahiro Kuroda2 1The University of Tokyo, Japan 2Research Association for Advanced Systems, Japan |
Session 16: Advanced Signal Generation and Radar Techniques
Session Chair: Kenichi Okada, Tokyo Institute of TechnologySession Co-chair: Howard Luong, Hong Kong University of Science and Technology
Date: Nov. 09, 2022 (Wednesday)
Time: 09:00 – 10:40 (UTC+8)
Room: Chang Chin 長青廳, 10F
| ID | Time | Title / Authors / Affiliation |
| 16.1 (7111) |
09:00 | 09:25 |
A Compact Square-Geometry Quad-Core 19 GHz Class-F
VCO with Parallel Inductor-sharing Technique achieving
-137.2 dBc/Hz Phase Noise at 10MHz Offset Yaqian Sun1, Wei Deng1,2, Haikun Jia1, Zhihua Wang1,2, and Baoyong Chi1 1Tsinghua University, China 2Research Institute of Tsinghua University in Shenzhen, China |
| 16.2 (7064) |
09:25 | 09:50 |
A 17-21GHz Current-Folding Frequency Tripler With
>36dBc Harmonic Rejection in 90nm CMOS Chun-Hung Lin and Ching-Yuan Yang National Chung Hsing University, Taiwan |
| 16.3 (7191) |
09:50 | 10:15 |
An 18.8-to-20.3-GHz Wide-Ramping-Range Cascaded-PLL-Based FMCW Generator with 44.1-kHz RMS
Frequency Error and -105.6-dBc/Hz Phase Noise in
40-nm CMOS Xiaofei Liao1,2, Feifan Hong1,2, Sijie Pan2, Xiaohu You1,2, and Dixian Zhao1,2 1Southeast University, China 2Purple Mountain Laboratories, China |
| 16.4 (7089) |
10:15 | 10:40 |
A 140GHz 4TX-4RX Phased-Array FMCW-FSK AntennaPackaged Radar Chipset With 25dBm EIRP and 16GHz BW Shunli Ma1, Tianxiang Wu1, Zhuofan Xu1, Zhonghao Sun1, Xuefeng Li1, Lei Wu1, Biao Hu1, Junyan Ren1, Yong Chen2, and Jiebin Pan3 1Fudan University, China 2University of Macau, China 3East China Institute of Photo-Electron IC, China |
Session 17: Emerging Circuit Techniques for Power Management, Sensing and Computing
Session Chair: Takuji Miki, Kobe UniversitySession Co-chair: Chihiro Okada, Sony Semiconductor Solutions Corporation
Date: Nov. 09, 2022 (Wednesday)
Time: 09:00 – 10:40 (UTC+8)
Room: V110 十全軒, VF
| ID | Time | Title / Authors / Affiliation |
| 17.1 (7236) (Highlight) |
09:00 | 09:25 |
A 14V Hybrid Boost Converter With Scalable Conversion
Ratio in 180nm Standard CMOS for an Ultrasound
Imaging System Jiaqi Guo1, Jiamin Li2, Jerald Yoo1,3 1National University of Singapore, Singapore 2Southern University of Science and Technology, China 3The N.1 Institute for Health, Singapore |
| 17.2 (7091) |
09:25 | 09:50 |
A 0.24 mmHg (1σ) Resolution Half-Bridge-to-Digital
Converter with RC Delay-Based Pressure Sensing and
Energy-Efficient Bit-Level Oversampling Techniques for
Implantable Miniature Systems Donguk Seo1, Minsik Cho1, Minhyeok Jeong1, Gicheol Shin1, Inhee Lee2, and Yoonmyung Lee1 1Sungkyunkwan University, Korea 2University of Pittsburgh, USA |
| 17.3 (7040) |
09:50 | 10:15 |
A 0.0308mm2 4.15pJ/conv VCO-Based Current Sensing Front-End with 2nd-Order Δ2-ΔΣ Modulation Jee-Ho Park, Ji-Hyoung Cha, Yongjae Park, and Seong-Jin Kim Ulsan National Institute of Science and Technology, Korea |
| 17.4 (7193) |
10:15 | 10:40 |
A 57.2GHz 11.2mW 8-bit General Purpose
Superconductor Microprocessor with Dual-Clocking
Scheme Ikki Nagaoka1, Ryota Kashima1, Tomoki Nakano1, Masamitsu Tanaka1, Taro Yamashita2, Koji Inoue3, and Akira Fujimaki1 1Nagoya University, Japan 2Tohoku University, Japan 3Kyushu University, Japan |
Session 18: Sensor Interfaces and References
Session Chair: Taekwang Jang, ETH, SwissSession Co-chair: Pieter Harpe, Eindhoven University of Technology
Date: Nov. 09, 2022 (Wednesday)
Time: 14:00 – 15:40 (UTC+8)
Room: Auditorium 國際會議廳, 10F
| ID | Time | Title / Authors / Affiliation |
| 18.1 (7080) (Highlight) |
14:00 | 14:25 |
A 0.56V/0.8V Vision Sensor with Temporal Contrast Pixel
and Column-Parallel Local Binary Pattern Extraction for
Dynamic Depth Sensing Using Stereo Vision Min-Yang Chiu, Guan-Cheng Chen, Yu-Hsiang Huang, Tzu-Hsiang Hsu, Chung-Chuan Lo, Ren-Shuo Liu, Meng-Fan Chang, Kea-Tiong Tang, Chih-Cheng Hsieh National Tsing Hua University, Taiwan |
| 18.2 (7150) |
14:25 | 14:50 |
A 118.6fJ/Conversion-Step Two-Step Time-Domain RCto-Digital Converter With 33nF/10MΩ Range and 53aFrms
Resolution Hoyong Seong1, Chongsoo Jung1, Donghyun Youn1,Junghyup Lee2, Sohmyung Ha3, and Minkyu Je1 1KAIST, Korea 2DGIST, Korea 3New York University Abu Dhabi, United Arab Emirates |
| 18.3 (7224) (Highlight) |
14:50 | 15:15 |
A −50 to 130 °C, 38.69 pJ/conv Fully Integrated SAR
Temperature Sensor Based on Direct Temperature-Voltage Comparison Jooeun Kim, Jeongmyeong Kim, Changjoo Park, Minkyu Yang, and Wanyeong Jung KAIST, South Korea |
| 18.4 (7020) |
15:15 | 15:27 |
A Digital Temperature Sensor Based on 10b SAR ADC for
Non-linear Temperature Dependency Compensation in
3D NAND Flash Memory Kyoung-Jun Roh, Min-Ki Jeon, Jaewoo Park, Myoungbo Kwak, Chi-Weon Yoon, Youngdon Choi and Jung-Hwan Choi Device Solutions, Samsung Electronics, Korea |
| 18.5 (7102) |
15:27 | 15:40 |
A sub-nW scalable nMOS voltage reference with multiloop regulation achieving 0.0126%/V line sensitivity Chutham Sawigun, Xiaolin Yang, Andrea Lodi, and Carolina Mora Lopez imec, Belgium |
Session 19: Imaging & Machine Learning Processing on FPGA
Session Chair: Tay-Jyi Lin, National Chung Cheng UniversitySession Co-chair: Ji-Hoon Kim, Ewha Womans University
Date: Nov. 09, 2022 (Wednesday)
Time: 14:00 – 15:40 (UTC+8)
Room: Song Bo 松柏廳, 10F
| ID | Time | Title / Authors / Affiliation |
| 19.1 (7217) |
14:00 | 14:25 |
A Real-Time High-Resolution Variable-Size Imaging
Processor for Spaceborne Synthetic Aperture Radar Jia-Zhao Lin1, Po-Ta Chen1, Hung-Yuan Chin1, Pei-Yun Tsai1, and Sz-Yuan Lee2 1National Central University, Taiwan 2National Applied Research Laboratory, Taiwan |
| 19.2 (7239) |
14:25 | 14:50 |
A 409.6 GOPS and 204.8 GFLOPS Mixed-Precision Vector
Processor System for General-Purpose Machine Learning
Acceleration Jung-Hoon Kim, Sukjin Lee, Seungjae Moon, Sungyeob Yoo, and Joo-Young Kim KAIST, Korea |
| 19.3 (7248) |
14:50 | 15:15 |
An Efficient Unsupervised Learning-based Monocular
Depth Estimation Processor with Partial-Switchable
Systolic Array Architecture in Edge Devices Wonhoon Park, Dongseok Im, Hankyul Kwon, and Hoi-Jun Yoo Korea Advanced Institute of Science and Technology, Korea |
| 19.4 (7235) |
15:15 | 15:40 |
F-LIC: FPGA-based Learned Image Compression with a
Fine-grained Pipeline Heming Sun1,2,3, Qingyang Yi4, Fangzheng Lin1, Lu Yu2, Jiro Katto1, and Masahiro Fujita4,5 1Waseda University, Japan 2Zhejiang University, China 3JST, PRESTO, Saitama, Japan 4The University of Tokyo, Japan 5AIST, Japan |
Session 20: Interfaces for High-Speed Memory
Session Chair: Chiweon Yoon, Samsung ElectronicsSession Co-chair: Pen-Jui Peng, National Tsing Hua University
Date: Nov. 09, 2022 (Wednesday)
Time: 14:00 – 15:40 (UTC+8)
Room: Chang Chin 長青廳, 10F
| ID | Time | Title / Authors / Affiliation |
| 20.1 (7104) (Highlight) |
14:00 | 14:25 |
A 0.95pJ/b 5.12Gb/s/pin Charge-Recycling IOs with 47%
Energy Reduction for Big Data Applications Han Wu1, Jeong Hoan Park2, Miaolin Zhang1, Longyang Lin3, Rucheng Jiang1, Jung-Hwan Choi2, Jerald Yoo1,4 1National University of Singapore, Singapore 2Samsung Electronics, South Korea 3Southern University of Science and Technology, China 4The N.1 Institute for Health, Singapore |
| 20.2 (7045) |
14:25 | 14:50 |
A 10Gb/s/pin DQS and WCK Built-Out Tester for LPDDR5
DRAM Test Chan-Ho Kye1, Jihee Kim2, Kyungmin Baek2, Kahyun Kim2, Sangjin Pack3, Changwon Jung3, and Deog-Kyoon Jeong2 1EPFL, Switzerland 2Seoul National University, Korea 3SK Hynix, Korea |
| 20.3 (7009) |
14:50 | 15:15 |
A 7.5Gb/s/pin 12Gb-LPDDR5x SDRAM with a Pseudodouble-bit ECC and “Spider”-shape Datapath Control Architecture in a 2nd Generation 10nm DRAM Process Feng Lin, Kangling Ji, Enpeng Gao, Zhonglai Liu, Weibing Shang, Hongwen Li Changxin Memory Technologies, Inc., China |
| 20.4 (7230) |
15:15 | 15:40 |
A Single-Ended Duobinary-PAM4(PAM7) Transmitter with
a 2-Tap Feed-Forward Equalizer Jaenam Kim1, 2*, Sanghyeon Park1, 2*, Jaewoo Park1, Junhan Bae1, and Jung-Hoon Chun1, 3 1Sungkyunkwan University, South Korea 2Samsung Electronics, South Korea 3SolidVue, South Korea *Equally Credited Authors (ECAs) |
Session 21: Application-Oriented ADCs
Session Chair: Chih-Cheng Hsieh, National Tsing Hua UniversitySession Co-chair: Shuang Zhu, NVIDIA
Date: Nov. 09, 2022 (Wednesday)
Time: 14:00 – 15:40 (UTC+8)
Room: V110 十全軒, VF
| ID | Time | Title / Authors / Affiliation |
| 21.1 (7112) (Highlight) |
14:00 | 14:25 |
A 91-dB DR 20-kHz BW 5th-Order Multi-Step Incremental
ADC for Sensor Interfaces by Re-Using a MASH 2-1
Modulator Jia-Sheng Huang1,2, Shih-Che Kuo1, Yu-Cheng Huang1, Chia-WeiKao1,2, Che-Wei Hsu1,3 and Chia-Hung Chen1 1National Yang Ming Chiao Tung University, Taiwan 2Now with Realtek, Taiwan 3Now with Mediatek, Taiwan |
| 21.2 (7165) |
14:25 | 14:50 |
A 78.6 dB-SNDR 520mVpp-full-scale 620MΩ-Zin 105dBCMRR VCO-based Sensor Readout Circuit Using FVFBased Gm-Input Structure Yi Zhong, Lu Jie, and Nan Sun. Tsinghua University, China |
| 21.3 (7043) |
14:50 | 15:15 |
110.1dB DR 4-ch Audio ADCs and 98dB DR 2-ch VoiceTriggering ADCs in Reconfigurable Architecture with
Enhanced Off-Transistor-Based Bias Noise Filter Moo-Yeol Choi, Inhwan Cho, Myungjin Lee, Seunghyun Oh, Jongwoo Lee Samsung Electronics, Korea |
| 21.4 (7219) |
15:15 | 15:27 |
A 103.8-dB DR 25ps-to-35ns Resolution Time-to-Digital
Converter with Dynamic Ring Oscillator for LiDAR
Applications Taewoong Kim1,2, Sanghoon Lee1, and Youngcheol Chae1 1Yonsei University, Korea 2Now in Samsung Electronics, Korea |
| 21.5 (7209) |
15:27 | 15:40 |
A 0.3V 762nW-Only Binary-Search Phase ADC With
Current-Reused RO-based Comparator Sifan Wang1, Kejin Li1, Chi-Hang Chan1, Yan Zhu1, Rui Paulo Martins1,2 1University of Macau, China 2On leave Universidade de Lisboa, Portugal |